Such circuit arrangements having a power transistor and a drive circuit with current sources for driving the power transistor are sufficiently known and, for example, are described in DE 198 55 604 C1.
During the switching of power transistors, voltage and current changes arise at the load and in the supply and connecting lines to the load and the power transistor, which changes lead to electromagnetic interference emissions. In order to avoid or reduce said interference emissions, it is known to flatten the voltage edges of a voltage that changes across the power transistor or across the load during switching by means of suitable driving of the power transistor. For this purpose, DE 198 55 604 C1 mentioned above discloses subdividing driving operations for on-state or off-state driving of the power transistor into different temporal phases during which different charging or discharging currents are made available for a drive electrode of the transistor. In order to define the beginning and end of these individual phases, a voltage across the load and a load current flowing through the load are compared with predetermined threshold values.
U.S. Pat. No. 4,540,893 likewise describes a circuit arrangement having a power transistor, a drive circuit for the power transistor and a load connected in series with the power transistor. This circuit arrangement takes account of a temporal change dI/dt in a load current I flowing through a load or a temporal change dV/dt in a voltage V across the load in the generation of a charging or discharging current of the power transistor.
For the purpose of driving a power transistor connected in series with a load with the aim of flattening the switching edges, DE 102 40 167 A1, moreover, provides a charging current or a discharging current which has a constant component and a component dependent on the voltage across the load. The variable component in each case counteracts the constant component and is related to the load voltage via a nonlinear characteristic curve, the variable component increasing continuously as the load voltage decreases. This has the effect that during off-state driving of the power transistor, the drive electrode thereof is initially discharged with a large discharging current and, as the voltage across the load decreases, is discharged with a continuously decreasing discharging current.
However, parasitic inductances of terminal lines can counteract the known measures for flattening the switching edges, as is explained below.
FIG. 1 shows a circuit arrangement having a power transistor T10 designed as a MOSFET, which has a gate terminal G and a drain-source path D-S, having a load Z connected in series with the load path D-S of the power transistor. The gate terminal G forms the control terminal and the drain-source path forms the load path of the transistor. The transistor T10 functions as a high-side switch whose drain terminal D is connected to a positive supply potential V1 via a power terminal and to whose source terminal S the load is connected, which is connected to a negative supply potential or reference-ground potential GND via a terminal remote from the transistor T10. The terminal line 1 has a parasitic inductance, designated by the reference symbol Lp in FIG. 1.
The transistor T1 inherently has a gate-source capacitance C1 and a drain-gate capacitance C2, which is also referred to as the Miller capacitance. The transistor T1 turns on if the gate-source capacitance C1 is charged to a value greater than the threshold voltage. In order to turn the transistor T1 off, said gate-source capacitance C1 has to be discharged with a suitable discharging current.
FIG. 2a schematically illustrates the temporal profile of a load current flowing through the transistor T1 and the load during such a turn-off operation for the transistor t1. In FIG. 2a, t1 designates an instant at which a fall in the load current commences proceeding from an initial value. This instant corresponds approximately to the instant at which the gate-source capacitance C1 is discharged to the value of the threshold voltage of the transistor by a discharging current Ig depicted in FIG. 1. t3 designates an instant at which the turn-off operation is concluded and the load current IL has fallen to zero.
The parasitic inductance Lp brings about a change in the drain potential Vd of the transistor T during the turn-off operation. This potential Vd corresponds to the supply potential V1 in the case of a transistor T1 that has already been switched on for a relatively long time. A deviation ΔVd=Vd−V1 of this drain potential Vd with respect to the supply potential V1 is in this case proportional to the temporal change dIL/dt in the load current IL. In this case, the proportionality factor is the inductance value of the parasitic inductance Lp. An instant at which this deviation reaches its maximum value is designated by t2 in FIG. 2. Via the Miller capacitance C2, this temporal change in the drain potential Vd leads to a parasitic current Ic2 to the gate electrode G from the gate electrode G which is proportional to a temporal change in the drain potential Vd. In this case, the proportionality factor corresponds to the value of the Miller capacitance C2. During a first time segment between the instants t1 and t2 between which the temporal change in the load current increases continuously, said parasitic current Ic2 counteracts the discharging current Ig and thereby slows down the discharge. During a second segment between the instants t2 and t3 between which the change in the load current decreases continuously up to the conclusion of the switch-off operation, the parasitic current Ic2 acts with the discharging current Ig and thereby accelerates the discharging of the gate-source capacitance.
However, it is precisely during this second time segment that a reduction of the discharging current is desirable, rather, in order to achieve a flattening of the load current curve. Thus, in particular, the drive circuit in accordance with DE 102 40 167 A1 mentioned above is designed to reduce the discharging current in the time segment shortly before the load current falls to zero. However, the parasitic effects explained counteract this reduction of the discharging current.